天利半導(dǎo)體集團(tuán)公司成立于2004年6月，總部位于美國(guó)，亞太營(yíng)運(yùn)中心位于香港，中國(guó)區(qū)總部位于深圳，是由美國(guó)硅谷集成電路設(shè)計(jì)資深專家創(chuàng)建以及來自北大、清華的數(shù)字、模擬電路的專家加盟，目前旗下全資子公司天利半導(dǎo)體（深圳）有限公司和北京方益集成電路設(shè)計(jì)有限公司。

天利半導(dǎo)體設(shè)計(jì)、開發(fā)、銷售平板顯示屏幕的驅(qū)動(dòng)芯片，其業(yè)務(wù)涵蓋集成電路設(shè)計(jì)的全部流程, 包括IC設(shè)計(jì)、工藝開發(fā)、IC封裝技術(shù)、IC測(cè)試、產(chǎn)品應(yīng)用開發(fā)、產(chǎn)品驗(yàn)證、特性化測(cè)試及失效分析。

天利半導(dǎo)體以市場(chǎng)需求為導(dǎo)向，結(jié)合公司的技術(shù)優(yōu)勢(shì)，相繼推出了系列MSTN、CSTN、TFT、OLED、TCON屏幕顯示驅(qū)動(dòng)芯片，并獲得多項(xiàng)國(guó)內(nèi)發(fā)明專利，各項(xiàng)技術(shù)指標(biāo)均達(dá)到同類國(guó)際知名品牌的標(biāo)準(zhǔn)，具有卓越的性價(jià)比。

天利半導(dǎo)體秉承“融資上下游產(chǎn)業(yè)，打造中國(guó)完整IC產(chǎn)業(yè)鏈”的企業(yè)發(fā)展戰(zhàn)略，全資收購(gòu)京東方旗下IC設(shè)計(jì)公司北京方益集成電路設(shè)計(jì)有限公司并與各大晶圓廠，封裝廠、模塊設(shè)計(jì)制造企業(yè)、終端制造商結(jié)成緊密的戰(zhàn)略伙伴合作和投資關(guān)系，形成市場(chǎng)、技術(shù)、資金、管理的良性互動(dòng)，實(shí)現(xiàn)產(chǎn)品在技術(shù)、價(jià)格、交付能力、客戶服務(wù)等方面的整體競(jìng)爭(zhēng)力，全力打造中國(guó)最大的TFT-LCD驅(qū)動(dòng)IC供貨商。
 
天利半導(dǎo)體現(xiàn)有如下職位空缺：
 
招聘職位：ASIC驗(yàn)證測(cè)試工程師
招聘人數(shù)： 3 人
有效時(shí)間： 2008-12-31
要求： ASIC驗(yàn)證測(cè)試部經(jīng)理Logic Verification Engineer
1)Job Function
A)In charge of verification and testing of ASIC chips.
B)Write test and verification spec for mixed signal chips.
C)Generate test and verification plan.
D)Manage a group of test and verification engineers.
2)Candidates must have the following qualifications.
A)At least 2 years RTL and Vera coding experience
B)Experience of managing a group of engineers..
C)Able to write and use test-bench to test RTL blocks.
D)Able to program FPGA to test logic blocks.
E)Must have strong logic thinking ability.
F)Strong ability to enforce methodology.
G)ASIC debugging experience preferred.

招聘職位：ASIC全定制版圖設(shè)計(jì)
招聘人數(shù)： 3 人
有效時(shí)間： 2008-12-31 
要求： ASIC全定制版圖設(shè)計(jì)VLSI Backend Design Engineer
1) Job Function
A) In charge of circuit custom layout design.
B) Responsible for block level floorplanning.
2) Candidates must have the following qualifications.
A) B.S Degree in EE or Computer Science. M.S. preferred.
B) 2-5 years experience in IC design.
C) Experienced in floor planning.
D) Familiar with cadence place and route tools.
E) Experienced in writing scripts for place and route.
F) Experienced in writing scripts for gate net-list synthesis.
G) Custom designed circuit layout experience.
H) Able to correctly model parasitic loading.
I) Aware of all the electric design issues involved including cross talk, IR drop, and electro-migration issues.

招聘職位：ASIC邏輯設(shè)計(jì)工程師 Logic Design Engineer
招聘人數(shù)： 5 人
有效時(shí)間： 2008-12-31
要求： 學(xué) 歷：本科
工作年限：二年以上
薪水范圍：面議
職位描述：
Job Function
A)Design digital circuit blocks using RTL coding in mixed signal IC chips.
B)Define micro architecture of digital part of the mixed signal IC.
Candidates must have the following qualifications.
A)2 years RTL coding experience
B)Understanding of concept of state-machine.
C)Understanding of the concept of timing. Able to perform static timing analysis.
D)Familiar with VCS or NC-Verilog
E)Able to write and use test-bench to test RTL blocks.
F)Able to program FPGA to test logic blocks.

招聘職位：IC模擬電路設(shè)計(jì)經(jīng)理
招聘人數(shù)： 3 人
有效時(shí)間： 2008-12-31
要求： Job Function
A)Design consumer electronics mixed signal IC
B)Responsible for product definition and micro architecture.
Candidates must have the following qualifications.
A)B.S Degree in EE or Computer Science. M.S. preferred.
B)Recent experience of designing TFT or STN LCD driver chip is preferred.
C)Aware of most of the issues involved including circuit design, module, glass panel, foundry interface, packaging, ESD design, testing.
D)Familiar with mixed signal design and verification flow.
E)Strong analog design background.
F)2-5 years experience in IC design.
G)Layout experienc(LVS/DRC)
H)Detailed knowledge of reference voltage circuit, dc-dc charge pump circuit, and oscillator circuit design.
I)Familiar with SPICE and mixed-signal simulation tools

招聘職位：ASIC邏輯設(shè)計(jì)經(jīng)理
招聘人數(shù)： 5 人
有效時(shí)間： 2008-12-31
要求： Job Function
A)Design digital circuit blocks using RTL coding in mixed signal IC chips.
B)Write RTL code for custom designed blocks such as SRAM and adder blocks.
C)Define micro architecture of digital part of the mixed signal IC.
D)Verification of the logic blocks using test bench and Vera.
E)Use FPGA to validate the designed blocks.
F)Write synthesis script to generate gate level netlist.
G)Analyze timing for synthesized blocks.
Candidates must have the following qualifications.
A)2 years RTL coding experience
B)Understanding of concept of state-machine.
C)Understanding of the concept of timing. Able to perform static timing analysis.
D)Familiar with VCS or NC-Verilog
E)Able to write and use test-bench to test RTL blocks.
F)Able to program FPGA to test logic blocks.

聯(lián)系人：金先生
http://www.tlsemi.com/html/appjob.php
EMAI：jinguohong@tlsemi.com