Vivace于2005年成立，致力于創(chuàng)造全新的安全視頻處理芯片，以滿足下一代用戶對電子產(chǎn)品的需求。通過對自定義處理器、高集成化固件以及硅驗證IP的結(jié)合，Vivace正努力創(chuàng)造出高性能芯片，滿足媒體處理器的高標準要求。

Vivace芯片可支持包括H264/MPEG4 AVC、MPEG4 ASP、Windows Media 9、MPEG2及VC-1在內(nèi)的多種視頻壓縮標準和包括AES、DES、3-DES及DVB CSA在內(nèi)的多種解碼標準。

因應業(yè)務發(fā)展需要，現(xiàn)在誠聘以下人員加盟：

  
招聘職位：模擬集成電路設計工程師（Analog IC Design Engineer）
職責：
模擬集成電路IP核設計，負責Video D/A轉(zhuǎn)換器、A/D轉(zhuǎn)換器、PLL等模擬IP的開發(fā)，包括技術規(guī)格定義，前后端設計，IP評價與標準化等。
要求：
（1）微電子或電子工程類專業(yè)
 (2) 熟悉CMOS 器件的設計和加工工藝
（3）熟悉模擬電路，參加過經(jīng)典模擬電路（Amplifier，ADC，DAC 或PLL等）的設計流程，熟悉音視頻領域的模擬電路（如Video D/A）設計者優(yōu)先考慮。
（4）精通模擬電路設計的基本工具，如HSPICE、SPECTRE、HSIM、Matlab等，熟悉IC設計流程的后端EDA工具
（5）具有較強的理解能力和協(xié)作能力。
Duties:
Responsible for analog IP core design such as Video D/A converter, PLL and A/D converter , including specification definition , front-end and back-end design, IP evaluation and standardize.
Requirements:
(1) Microelectronic or electronic engineering major ;
(2)Familiar with CMOS devices’ design and process technologies;
(3) familiar with analog circuits, participated design flow of typical circuit designs (such as Amplifier, ADC, DAC or PLL, etc.), the candidate familiar with Audio/Video analog circuit (such as Video DAC or PLL) will be given priority.
(4) Skillfully use basic EDA software and analysis tools for analog domain, such as HSPICE, Spectre, HSIM, MatLab, etc, familiar with back-end design tools ;
(5) Good understanding and cooperation? spirit.
 

招聘職位：數(shù)字前端設計工程師（Digital FE Design Engineer）
職責：
負責面向SoC應用的CPU核及其周邊模塊的前端電路設計、功能與時序驗證、可測性設計；配合后端設計工程師實現(xiàn)數(shù)字模塊的時序收斂與功耗收斂。
要求：
（1）電子工程或計算機專業(yè)本科以上學歷；
（2）熟悉前端設計的整個開發(fā)流程及相關EDA工具（Simulation、Synthesis 和Timing Analysis）；熟練掌握Verilog等設計語言；有較強的系統(tǒng)設計和數(shù)字邏輯電路設計能力。
（3）熟悉通用微處理器體系結(jié)構(gòu)及其驗證環(huán)境，有RISC CPU、LCD Controller等設計經(jīng)驗者優(yōu)先考慮，
（4）具有較強的、理解能力和協(xié)作能力。
Duties:
Responsible for front-end design, functional and timing verification, and testing design of CPU core and peripherals for SoC application. A candidate needs to coordinate with back-end design engineers toward a closure of digital module’s timing and power convergence.
Requirements:
(1) BS of electronic engineering , computer science, or above ;
(2)Familiar with front-end design flow and EDA tools (relating to simulation, synthesis and timing analysis); Skillfully use Verilog hardware description language; Have strong ability of system and digital logic design;
(3) Familiar with the architecture of universal micro processor as well as its verification environment, the candidate who has design experience of RISC CPU or LCD controller will be given priority;
(4)Good understanding and cooperation? spirit.
 

招聘職位：DSP技術支持工程師（DSP Application Engineer）
職責：
負責先進的DSP核銷售技術支持；幫助客戶利用DSP技術和工具開發(fā)客戶產(chǎn)品。
要求：
（1）電子工程或計算機專業(yè)本科以上學歷；
（2）熟悉DSP應用，具有DSP領域的開發(fā)經(jīng)驗；
（3）了解基本的IC設計流程，使用過硬件描述語言Verilog
（4）有較強的學習能力，理解能力和協(xié)作能力。
（5）良好的英語能力，能夠閱讀和書寫英文技術文檔
（6）熟悉Java、Jbuilder和VLIW體系結(jié)構(gòu)者優(yōu)先考慮。
Duties:
Responsible for sales support of an advanced DSP core, help customers smoothly employ our DSP technology and tool suite to develop their products.
Requirements:
(1) BS of electronic engineering , computer science, or above ;
(2)Familiar with DSP application, have development experience relating to DSP ; (3) Understand basic IC design flow, be capable to use hardware description language Verilog ;
(4) Strong ability of study，good understanding and cooperation spirit.
(5) Good English knowledge, be capable to read and write technical documents;
(6)The candidate familiar with Java, Jbuilder and VLIW architecture will be given priority
 

招聘職位：SoC集成支持工程師（SoC Integration Engineer）
職責：
負責SoC集成技術支持；幫助客戶基于CPU或DSP技術平臺開發(fā)客戶的SoC產(chǎn)品。
要求：
（1）電子工程或計算機專業(yè)本科以上學歷；
（2）熟悉以IP為基礎的SoC集成方案，熟悉DSP應用和CPU平臺應用技術；
（3）熟悉SoC設計流程和RTL設計
（4）有較強的學習能力，理解能力和協(xié)作能力。
（5）良好的英語能力，能夠閱讀和書寫英文技術文檔。
Duties:
Responsible for technical support of SoC integration, help customers develop their SoC products based on our CPU or DSP technology platform.
Requirements:
(1) BS of electronic engineering , computer science, or above ;
(2)Familiar with IP-based SoC integration solution, familiar with DSP and CPU platform application;
(3) Familiar with SoC? design flow and RTL deisgn ;
(4) Strong ability of study，good understanding and cooperation spirit.
(5) Good English knowledge, be capable to read and write technical documents.
 

招聘職位：應用工程師（Application Engineer）
職責：
負責公司VSP產(chǎn)品的應用技術支持。包括
（1）針對產(chǎn)品的應用方案，支持從芯片產(chǎn)品的開發(fā)系統(tǒng)、參考系統(tǒng)、應用系統(tǒng)到客戶（系統(tǒng)設計公司）的過程；
（2）對市場部門運作提供技術支持；
（3）相關產(chǎn)品技術調(diào)研等等。
要求：
熟悉系統(tǒng)級設計流程；熟練使用Cadence OrCAD/Allegro流程進行系統(tǒng)級設計；了解基于32位嵌入式SoC芯片搭建的系統(tǒng)；了解視頻編解碼相關芯片使用；了解電源管理芯片的使用；有廣泛的應用工程知識，能與軟、硬件設計，用戶界面設計、安規(guī)測試、結(jié)構(gòu)設計等專業(yè)人員溝通和交流。熟悉音視頻DSP器件和手持系統(tǒng)設計和應用者優(yōu)先
Duties:
Responsible for SoC product applications and technical supports. Oriented to SoC products’ application solutions, with supporting activities range from the chip’s development system, reference system, application system, customers (system design house) designs through entire design chain and industrial processes;
Requirements:
Familiar with system-level design flow; master cadence OrCAD/Allegro tool for system-level designs; master system integration which is based on a 32-bit embedded SoC; understand video codec chips’ applications; understand power management components’ applications and their PCB level solutions. The candidate should possess a broad range of experience in application engineering and ability to communicate effectively with professionals who engage in hardware, software design, user interface design, safety test and structure design. A candidate should be rich in hands-on design and assembly experience, skillfully uses logic analyzer, oscillograph, etc. Ones who are familiar with A/V DSP devices and application of FPGA will be much preferred.

 
招聘職位：嵌入式軟件工程師（Embedded System Software Engineer）
職責：
負責開發(fā)使用公司VSP產(chǎn)品的不同系統(tǒng)上的相關軟件；包括Linux操作系統(tǒng)、驅(qū)動程序、專用測試程序和應用軟件；針對不同的用戶方案，進行相關項目的軟件開發(fā)，包括驅(qū)動程序以及針對專用協(xié)議（比如 移動電視標準）的軟件設計；和嵌入式系統(tǒng)設計工程師配合完成系統(tǒng)的聯(lián)調(diào)。
要求：
精通C/C++語言；熟悉嵌入式Linux操作系統(tǒng)或Windows CE操作系統(tǒng)，有操作系統(tǒng)優(yōu)化、裁減等項目經(jīng)驗；有通用應用軟件（比如UI）開發(fā)經(jīng)驗；有基于嵌入式操作系統(tǒng)的驅(qū)動程序開發(fā)經(jīng)驗；對通用硬件平臺（比如 ARM）有一定使用基礎；熟練使用相對應的開發(fā)與調(diào)試工具；熟悉團隊開發(fā)工具與版本控制工具的使用；熟悉網(wǎng)絡與音視頻相關DSP數(shù)據(jù)標準與開發(fā)者優(yōu)先。
Duties:
Develop embedded software for the company’s proprietary SoC products. Software work involves operation system, driver programs, dedicated test and benchmark, upon application software. Assist and coordinate system engineers’ and IC designers’ development work, together accomplish implementation and test of a system product (solutions, applications and prototypes);
Requirements:
Being skillful in C/C++ programming, familiar with embedded Linux or Windows CE operating systems, skillfully uses related development and debugging tools. The candidate should be understating and being familiar with principle and operations of processor development systems, master program and data version control tools. Familiarity with network and A/V DSP data standards is preferred
 

招聘職位：嵌入式系統(tǒng)硬件設計工程師（Embedded Hardware System Design Engineer）
職責：
負責設計基于公司SoC產(chǎn)品，針對不同應用的板級解決方案；配合SoC產(chǎn)品開發(fā)與測試設計相關電路。完成從產(chǎn)品方案制訂到系統(tǒng)級原理圖設計的全過程；配合PCB布線工程師完成符合時序與功耗要求的PCB設計；配合嵌入式軟件工程師與SoC設計工程師完成軟硬件的聯(lián)合調(diào)試。
要求：
熟悉系統(tǒng)級設計流程；熟練使用Cadence OrCAD/Allegro流程進行系統(tǒng)級設計；了解基于32位嵌入式SoC芯片搭建的系統(tǒng)；了解電源管理芯片的使用；豐富的動手調(diào)試經(jīng)驗；熟練使用邏輯分析儀、示波器等測試手段進行硬件調(diào)試。熟悉音視頻DSP器件和FPGA應用者優(yōu)先。
Duties:
Develop systems based on the company’s SoC products, towards the products’ various PCB-level solutions. Cooperate with SoC product designers in test fixture development. Accomplish entire solution developments, from specifications to system design; cooperate with PCB layout engineers to complete designs that fulfill targeted timing and power performance. Cooperate with embedded software engineers and SoC engineers to accomplish hardware/software joint implementation.
Requirements:
Familiar with system-level design flow; master cadence OrCAD/Allegro tool for system-level designs; master system integration which is based on a 32-bit embedded SoC; understand power management components’ applications and their PCB level solutions. A candidate should be rich in hands-on design and assembly experience, skillfully uses logic analyzer, oscillograph, etc. Ones who are familiar with A/V DSP devices and application of FPGA will be much preferred
 

招聘職位：算法工程師（Algorithm Engineer）
職責：
負責通信系統(tǒng)基帶算法的設計、優(yōu)化；對硬件實現(xiàn)及系統(tǒng)應用過程進行支持，協(xié)助完成測試驗證。
要求：
通信、電子及相關專業(yè)碩士；精通信號處理知識，具有一定的理論基礎；熟練使用matlab，熟悉JAVA、C語言；兩年以上移動通信系統(tǒng)開發(fā)經(jīng)驗；有DSP開發(fā)經(jīng)驗或熟悉verilog尤佳；具備良好的英語讀寫能力，有良好的團隊合作及鉆研精神。
Duties:
Responsible for designing and optimization of communication baseband signal processing algorithm, supporting the hardware designing and system application, assisting relational testing, verification;
Requirements:
MS. in EE, communication or related engineering fields; familiar with algorithms of signal processing; hands-on with Matlab, familiar with C, JAVA; at least 2 years experiences in mobile communication system development; knowledge on DSP, verilog , is a plus ; excellent English communication skills, be good at English reading
 

招聘職位：系統(tǒng)工程師(軟件)（System Engineer (software)）
職責：
完成通信系統(tǒng)中軟件部分的程序設計；搭建完整的系統(tǒng)開發(fā)、驗證環(huán)境；完成軟件及硬件代碼的協(xié)同驗證；負責項目開發(fā)過程中的版本管理。
要求：
計算機、電子、通信及相關專業(yè)碩士；有一年以上實際的通信系統(tǒng)項目經(jīng)驗，精通C、JAVA；對ARM開發(fā)，常見總線接口如I2C、SPI有一定了解；熟悉verilog尤佳；具備良好的英語讀寫能力，有良好的團隊合作及鉆研精神。
Duties:
Responsible for designing software part in communication system; constructing testing flat, performing? system verifying and version controlling.
Requirements:
MS. in computer science ,EE, communication or related engineering fields; have practical experience in communication development; familiar with C, JAVA; knowledge on ARM development.I2C, SPI etc; knowledge on? verilog , is a plus ; excellent English communication skills, be good at English reading.
 

招聘職位：高級數(shù)字前端設計工程師（Digital Front-end Design Engineer）
職責：
負責通信系統(tǒng)復雜數(shù)字模塊的RTL生成、功能驗證；配合后端設計工程師實現(xiàn)數(shù)字模塊的時序收斂與功耗收斂。
要求：
電子、通信及相關專業(yè)碩士；兩年以上工作經(jīng)驗；熟練使用Verilog硬件描述語言進行可綜合設計；了解ESL描述與驗證；能熟練使用主流設計工具完成復雜數(shù)字模塊的設計與驗證；有復雜數(shù)字系統(tǒng)的FPGA實現(xiàn)經(jīng)驗,具備良好的英語讀寫能力，有良好的團隊合作及鉆研精神。
Duties:
Responsible for front-end design, functional verification. coordinate with back-end design engineers toward a closure of digital module’s timing and power convergence.
Requirements:
MS. in computer science ,EE, communication or related engineering fields;? skillfully use Verilog hardware description language for logic design and synthesize; understand ESL descriptions and related verification, can skillfully use mainstream design tools for accomplishing complex digital modules’design and verification
 
 
招聘職位：數(shù)字前端設計工程師（Digital Front-end Design Engineer)
職責：
負責通信系統(tǒng)復雜數(shù)字模塊的RTL生成、功能驗證。
要求：
電子、通信及相關專業(yè)學士；一年以上工作經(jīng)驗；熟練使用Verilog硬件描述語言進行可綜合設計；能熟練使用主流設計工具完成數(shù)字模塊的設計與驗證,具備良好的英語讀寫能力，有良好的團隊合作及鉆研精神。
Duties:
Responsible for front-end design, functional verification.
Requirements:
Bachelor in computer science ,EE, communication or related engineering fields; one year practical experience,? skillfully use Verilog hardware description language for logic design and synthesizable ; can skillfully use mainstream design tools for accomplishing digital modules’ design and verification
 
 
招聘職位：系統(tǒng)工程師（System Engineer）
職責：
完成基帶芯片外圍接口設計，與后端工程師配合完成基于FPGA的測試驗證。
要求：
電子、通信及相關專業(yè)學士；兩年以上工作經(jīng)驗；對模擬芯片及ADC的各種參數(shù)有一定了解；熟悉常見的接口協(xié)議如I2C、SPI等，熟練使用Verilog硬件描述語言，對數(shù)字系統(tǒng)的FPGA驗證有所了解,具備良好的英語讀寫能力，有良好的團隊合作及鉆研精神。
Duties:
Responsible specifying IO of baseband processor, coordination with back-end engineer to?? accomplish verifying on FPGA.
Requirements:
Bachelor in computer science ,EE, communication or related engineering fields; two year practical experience; familiar with? general parameters of RF chip and ADC; knowledge on I2C,SPI etc.;? familiar with verilog ; good knowledge on verifying on FPGA is a plus ; excellent English communication skills, be good at English reading.
 

了解進一步信息，請訪問http://www.vivace.com.cn/job/job.html，或聯(lián)系Vivace公司：
E-mail: job@vivace.com.cn
聯(lián)系電話: 82358482-620